Timing Optimization through Pipelining And
نویسندگان
چکیده
In this paper, we consider the use of a limited pipelining scheme in conjunction with a gate resizing technique to improve the optimal clock speed of a combinational logic block. Gate resizing is restricted to a small subset of the circuit, and target gates are identiied using a delay sensitivity metric introduced here. 1 Abstract In this paper, we consider the use of a limited pipelining scheme in conjunction with a gate resizing technique to improve the optimal clock speed of a combinational logic block. Gate resizing is restricted to a small subset of the circuit, and target gates are identiied using a delay sensitivity metric introduced here.
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